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Freescale Semiconductor /MKW21Z4 /DCDC /REG0

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Interpret as REG0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DCDC_DISABLE_AUTO_CLK_SWITCH)DCDC_DISABLE_AUTO_CLK_SWITCH 0 (DCDC_SEL_CLK)DCDC_SEL_CLK 0 (DCDC_PWD_OSC_INT)DCDC_PWD_OSC_INT 0 (DCDC_LP_DF_CMP_ENABLE)DCDC_LP_DF_CMP_ENABLE 0DCDC_VBAT_DIV_CTRL 0 (00)DCDC_LP_STATE_HYS_L 0 (00)DCDC_LP_STATE_HYS_H 0 (HYST_LP_COMP_ADJ)HYST_LP_COMP_ADJ 0 (HYST_LP_CMP_DISABLE)HYST_LP_CMP_DISABLE 0 (OFFSET_RSNS_LP_ADJ)OFFSET_RSNS_LP_ADJ 0 (OFFSET_RSNS_LP_DISABLE)OFFSET_RSNS_LP_DISABLE 0 (DCDC_LESS_I)DCDC_LESS_I 0 (PWD_CMP_OFFSET)PWD_CMP_OFFSET 0 (DCDC_XTALOK_DISABLE)DCDC_XTALOK_DISABLE 0 (PSWITCH_STATUS)PSWITCH_STATUS 0 (VLPS_CONFIG_DCDC_HP)VLPS_CONFIG_DCDC_HP 0 (VLPR_VLPW_CONFIG_DCDC_HP)VLPR_VLPW_CONFIG_DCDC_HP 0 (DCDC_STS_DC_OK)DCDC_STS_DC_OK

DCDC_LP_STATE_HYS_H=00, DCDC_LP_STATE_HYS_L=00

Description

DCDC REGISTER 0

Fields

DCDC_DISABLE_AUTO_CLK_SWITCH

Disable automatic clock switch from internal oscillator to external clock.
DCDC_SEL_CLK

Select external clock for DCDC when DCDC_DISABLE_AUTO_CLK_SWITCH is set.
DCDC_PWD_OSC_INT

Power down internal oscillator. Only set this bit when 32M crystal oscillator is available.
DCDC_LP_DF_CMP_ENABLE

Enable low power differential comparators, to sense lower supply in pulsed mode
DCDC_VBAT_DIV_CTRL

Controls VBAT voltage divider
DCDC_LP_STATE_HYS_L

Configure the hysteretic lower threshold value in low power mode

0 (00): Target voltage value - 0 mV

1 (01): Target voltage value - 25 mV

2 (10): Target voltage value - 50 mV

3 (11): Target voltage value - 75 mV
DCDC_LP_STATE_HYS_H

Configure the hysteretic upper threshold value in low power mode

0 (00): Target voltage value + 0 mV

1 (01): Target voltage value + 25 mV

2 (10): Target voltage value + 50 mV

3 (11): Target voltage value + 75 mV
HYST_LP_COMP_ADJ

Adjust hysteretic value in low power comparator.
HYST_LP_CMP_DISABLE

Disable hysteresis in low power comparator.
OFFSET_RSNS_LP_ADJ

Adjust hysteretic value in low power voltage sense.
OFFSET_RSNS_LP_DISABLE

Disable hysteresis in low power voltage sense.
DCDC_LESS_I

Reduce DCDC current. It will save approximately 20 uA in RUN.
PWD_CMP_OFFSET

Power down output range comparator
DCDC_XTALOK_DISABLE

Disable xtalok detection circuit.
PSWITCH_STATUS

Status register to indicate PSWITCH status
VLPS_CONFIG_DCDC_HP

Selects behavior of DCDC in device VLPS low power mode
VLPR_VLPW_CONFIG_DCDC_HP

Selects behavior of DCDC in device VLPR and VLPW low power modes
DCDC_STS_DC_OK

Status register to indicate DCDC lock

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data